library ieee;

use ieee.std_logic_1164.all;

entity MANSYUR is

port (CLK, RESET, D : in std_logic;

Q : out std_logic);

end MANSYUR;

architecture MANSYUR of PFF_RST is

begin

DFF_PROCESS: process (CLK, RESET)

begin

if (RESET = ‘1’) then

Q <= ‘0’;

elsif (CLK’event and CLK = ‘1’) then

Q <= D;

end if;

end process;

end MASYUR;

library ieee;

use ieee.std_logic_1164.all;

use work.and2in_pkg.all;